1. Field of the Invention
This invention relates to NOR gate circuits, particularly decoder circuits with large fan-in for use in integrated circuits including memories and processors.
2. Description of the Related Art
A decoder uses one or more binary values, or addresses, to select between a number of outputs and to assert the selected output by placing it in its active state. Decoders can be constructed using a variety of logic gates. Decoders are commonly used in a wide variety of applications including, for example, interfacing to microprocessors to trigger different actions depending on the address; enabling a sequence of actions in turn according to an advancing address given by the output of a binary counter; and selecting individual memory elements, rows (word lines), or columns (bit lines) of memory arrays. Depending upon the application, decoders may be large, with a large number of address lines going into the decoder (i.e. large fan-in) and a correspondingly large number of decode lines going out of the decoder. For example, a 4:16 decoder has four address select inputs and sixteen decode outputs.
Additionally, circuit designers seeking to improve and extend the capabilities of integrated circuits, including memories an processors, have used a variety of decoder designs in order to improve execution speed, reduce power consumption, and reduce circuit size.
FIG. 1 is an example of a 2:4 NAND decoder, so called because of its use of NAND gates to accomplish the decoding function. Examples discussed in this specification will focus on 2:4 decoders for simplicity's sake. The decoder has two address input lines A and B and four decode lines R1, R2, R3, and R4. Complements of the input signals are produced by inverters 102 and 104. If signals A and B both represent a logic 0, (00 being the address for decode line R1) then NAND gate 106 receives logic 1 at both of its inputs and produces a logic 0 signal as output. Thus, this device is said to be active-low, because the active state is logic 0. Inverter 108 inverts the signal producing a logic 1 state at R1. Under the same input conditions, the remaining NAND gates resolve to logic 1, which in turn is inverted to the logic 0 state at decode outputs R2-R4. Similarly, inputs of 01, 10, and 11 would produce the logic 1 state at outputs R2, R3, and R4, respectively. This NAND decoder scheme is often referred to as a one-hot-decode because only one decode output (the selected output) is in the logic 1 state.
FIG. 2 shows an example of a dynamic logic implementation for the NAND gate and inverter 110 of FIG. 1. In operation of this circuit, when the clock signal .phi. is low (precharge phase), PMOS transistor 202 is conducting while the complementary NMOS transistor 204 is off, and the decode output line is precharged to the logic-high level of V.sub.DD. When the clock signal .phi. becomes high (evaluate phase), the precharge transistor 202 turns off and transistor 204 turns on. As in the example given above, if both input signals A and B represent a logic 0, there complements will be logic 1, and both NMOS transistors 206 and 208 are turned on. With both transistor 206 and 208 turned on, NAND output node 210 is pulled to the logic-low level of ground. Inverter 108 inverts the signal producing a logic 1 state at R1.
Dynamic logic NAND gates are often used in decoders because of the inherent high-speed of dynamic logic. In the examples above, 2:4 NAND decoders are shown, but as larger decoders are desired, the number of fan-ins on each NAND gate also increase. Thus, for a 4:16 NAND decode, two additional NMOS transistors are added to the stack, in series with transistors 206 and 208. However, as more transistors are added to the stack, the resistance of the pull down path increases because there are more transistors. The added resistance in turn makes the response of the NAND gate slower. Alternatively, as transistors are added to the stack, the size of the transistors increases to reduce the resistance of each individual transistor while keeping the overall resistance of the stack constant. However, larger transistors consume more space and lead to larger input capacitances which slow the circuit's response. Moreover, each additional transistor in a stack has a voltage drop across it, and so the top transistors in the stack have increasingly higher source voltages during switching and correspondingly deteriorated switching performance.
One solution to these problems associated with increased fan-in is to shift from a NAND decoder to a NOR decoder. FIG. 3 illustrates a prior art 2:4 NOR decoder. The decoder has two address input lines A and B and four decode lines R1, R2, R3, and R4. Complements of the input signals are produced by inverters 302 and 304. If signals A and B both represent a logic 0, (00 being the address for decode line R1) then NOR gate 306 receives logic 0 at both of its inputs and produces a logic 1 signal as output. Thus, this device is said to be active-high, because the active state is logic 1. Under the same input conditions, the remaining NOR gates resolve to logic 0, at decode outputs R2-R4. Similarly, inputs of 01, 10, and 11 would produce the logic 1 state at outputs R2, R3, and R4, respectively. This NOR decoder scheme is also referred to as a one-hot-decode because only one decode output (the selected output) is in the logic 1 state.
FIG. 4 shows an example of a dynamic logic implementation for the NOR gate 306 of FIG. 3. In operation of this circuit, when the clock signal .phi. is low (precharge phase), PMOS transistor 402 is conducting and the decode output line is precharged to the logic-high level of V.sub.DD. When the clock signal .phi. becomes high (evaluate phase), the precharge transistor 402 turns off. As in the example of the NOR decoder given above, if both input signals A and B represent a logic 0, both NMOS transistors 406 and 408 are turned off. With both transistors 406 and 408 turned off, NOR output node 410 and decode line R1 (buffered by inverters 412 and 414) remain at the logic-high level of V.sub.DD.
A NOR decoder has several advantageous characteristics. For larger decodes, additional fan-ins are added to the NOR gates. Thus, for a 4:16 NOR decoder, two additional NMOS transistors are added in parallel with transistors 406 and 408. Because the transistors are added in parallel, the total resistance encountered during the evaluate phase does not increase, and the NOR decoder resolves more quickly than the NAND decoder.
Dynamic NOR gates used in a decode circuit have a significant drawback. During the precharge phase, PMOS transistor 402 is conducting and the decode output line is precharged to the logic-high level. Thus, during the precharge phase, all of the decode outputs R1-R4 are high, thereby violating the one-hot-decode condition as seen in the aforementioned NAND decoder. This feature is undesirable for a variety of reasons. For example, if the decoder is used to address a random access memory (RAM) array, the prior art NOR decoder has a precharge phase with all of the word lines asserted, thereby decoding all of the word lines at a time when decode is not requested. Additionally, asserting all of the decode lines during precharge can short all of the memory cells together, thereby leading to data corruption.
Accordingly, it is desirable to have a circuit that has the advantages previously discussed, while at the same time ensuring that, during a precharge phase, the output of the NOR gate is inactive.